The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Mar. 24, 2014
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Bernd Landgraf, St. Martin, AT;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 29/94 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 21/28273 (2013.01); H01L 28/60 (2013.01); H01L 29/66181 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/7883 (2013.01); H01L 29/94 (2013.01);
Abstract

A semiconductor device is provided, which may include: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate and electrically coupled to the well; and a control gate terminal electrically coupled to the control gate; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage.


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