The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Dec. 16, 2015
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza (MB), IT;

Inventors:

Francesca Grande, Syracuse, IT;

Alfredo Signorello, Tremestieri Etneo Catania, IT;

SantiNunzioAntonino Pagano, Catania, IT;

Maria Giaquinta, Catania, IT;

Assignee:

STMICROELECTRONICS S.R.L., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 16/14 (2006.01); G11C 16/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/08 (2013.01);
Abstract

A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.


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