The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

May. 14, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventor:

Taihei Shido, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/4093 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 7/1006 (2013.01); G11C 7/1096 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); G11C 29/44 (2013.01); G11C 7/1087 (2013.01);
Abstract

Embodiments of the present invention relate to a latch circuit (L) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF) which outputs the data mask signal (DM) that has been latched by the latch circuit (L), said data mask signal (DM) being output in response to a write clock signal (WCLK); and a main amplifier () which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.


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