The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 07, 2017

Filed:

Mar. 14, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chin-Hsiung Hsu, Guanyin Township, TW;

Li-Chun Tien, Tainan, TW;

Pin-Dai Sue, Tainan, TW;

Ching Hsiang Chang, New Taipei, TW;

Wen-Hao Chen, Hsin-Chu, TW;

Cheng-I Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 7/20 (2006.01); G03F 1/70 (2012.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G03F 1/70 (2013.01); G03F 7/70433 (2013.01); G03F 7/70466 (2013.01);
Abstract

A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.


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