The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2017
Filed:
Nov. 11, 2015
Xilinx, Inc., San Jose, CA (US);
Anna W. Wong, Palo Alto, CA (US);
Ankur Jain, Sunnyvale, CA (US);
Richard W. Swanson, San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.