The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2017
Filed:
Jan. 22, 2016
Altera Corporation, San Jose, CA (US);
Weimin Zhang, San Jose, CA (US);
Yanzhong Xu, Santa Clara, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.