The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Jul. 19, 2016
Applicant:

Alps Electric Co., Ltd., Tokyo, JP;

Inventors:

Junichi Saito, Miyagi-ken, JP;

Tomoyuki Sawataishi, Miyagi-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/082 (2006.01); H03K 17/0812 (2006.01); H01L 27/092 (2006.01); H03K 17/16 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H03K 17/08122 (2013.01); H01L 27/092 (2013.01); H01L 29/7817 (2013.01); H03K 17/0822 (2013.01); H03K 17/161 (2013.01);
Abstract

A semiconductor integrated circuit device is configured such that if, due to an erroneous connection or the like, an abnormal state is entered in which an output voltage is lower than a ground potential VSS, an N-type DMOS transistor and a first P-type MOS transistor are turned off and a voltage is applied to their parasitic diodes in the opposite direction, preventing a current from flowing. In a normal state in which the output voltage is higher than the ground potential, at least one of the N-type DMOS transistor and first P-type MOS transistor, which are connected in parallel, is turned on, preventing a current from flowing into the parasitic diode of the N-type DMOS transistor.


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