The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2017
Filed:
Apr. 15, 2013
Applicant:
Marvell International Ltd., Hamilton, BM;
Inventors:
Vinay Chitturi, Sunnyvale, CA (US);
Oscar M. Siguenza, San Jose, CA (US);
Assignee:
Marvell International Ltd., Hamilton, BM;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/289 (2006.01); H03K 3/286 (2006.01);
U.S. Cl.
CPC ...
H03K 3/289 (2013.01); H03K 3/286 (2013.01);
Abstract
In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.
Chitturi, Vinay. (2017). Ser tolerant flip flop having a redundant latch (U.S. Patent No. 9559672). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9559672
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile