The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Mar. 19, 2015
Applicant:

Upi Semiconductor Corp., Zhubei, Hsinchu County, TW;

Inventors:

Cheng-Ching Hsu, Zhubei, TW;

Yen-Hsun Wang, Zhubei, TW;

Assignee:

UPI SEMICONDUCTOR CORPORATION, Zhubei, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01); G05F 1/33 (2006.01); H02M 3/158 (2006.01); G06F 1/32 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); G06F 1/3203 (2013.01); H02M 2001/0032 (2013.01); Y02B 70/16 (2013.01);
Abstract

A power managing apparatus, a DC-DC control circuit, and a method for enabling a chip are disclosed. The power managing apparatus has an enable pin and the enable pin is used to couple a first level control circuit. The power managing apparatus includes a second level control circuit and a level detecting circuit. The second level control circuit is coupled to the enable pin. The level detecting circuit is coupled to the enable pin and used to detect a control signal on the enable pin. The control signal is transmitted from the first level control circuit. The control signal has at least three levels according to operations of the first level control circuit and the second level control circuit.


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