The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Dec. 30, 2014
Applicant:

Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;

Inventors:

Daisuke Inoue, Cheonan-si, KR;

Mi Suk Kim, Cheonan-si, KR;

Si Heun Kim, Hwaseong-si, KR;

Tae Ho Kim, Asan-si, KR;

So Youn Park, Hwaseong-si, KR;

Keun Chan Oh, Cheonan-si, KR;

Chang-Hun Lee, Hwaseong-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); H01L 27/12 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/417 (2006.01); G02F 1/1365 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1365 (2013.01); G02F 1/133345 (2013.01); H01L 29/41733 (2013.01); H01L 29/4908 (2013.01); H01L 29/517 (2013.01);
Abstract

A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on the gate line and the first electrode; a data line on the gate insulating layer; a passivation layer on the gate insulating layer and the data line; and a second electrode on the passivation layer. Relative permittivity (ε) of the gate insulating layer is more than about 15, and a thickness of the gate insulating layer is about 2000 angstroms.


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