The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Jul. 01, 2015
Applicant:

Skyworks Solutions, Inc., Woburn, MA (US);

Inventors:

Peter J. Zampardi, Newbury Park, CA (US);

Hsiang-Chih Sun, Thousand Oaks, CA (US);

Assignee:

SKYWORKS SOLUTIONS, INC., Woburn, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 29/737 (2006.01); H01L 29/812 (2006.01); H01L 29/08 (2006.01); H01L 29/205 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0623 (2013.01); H01L 29/0817 (2013.01); H01L 29/205 (2013.01); H01L 29/66318 (2013.01); H01L 29/66462 (2013.01); H01L 29/7371 (2013.01); H01L 29/812 (2013.01); H03F 3/195 (2013.01); H03F 3/245 (2013.01);
Abstract

A semiconductor structure includes a heterojunction bipolar transistor (HBT) including a collector layer located over a substrate, the collector layer including a semiconductor material, and a field effect transistor (FET) located over the substrate, the FET having a channel formed in the semiconductor material that forms the collector layer of the HBT. In some implementations, a second FET can be provided so as to be located over the substrate and configured to include a channel formed in a semiconductor material that forms an emitter of the HBT. One or more of the foregoing features can be implemented in devices such as a die, a packaged module, and a wireless device.


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