The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Sep. 11, 2012
Applicants:

Seng-teong Chang, Penang, MY;

Choon Keat OR, Penang, MY;

Wai-choo Chai, Penang, MY;

Chong-tee Ong, Penang, MY;

Inventors:

Seng-Teong Chang, Penang, MY;

Choon Keat Or, Penang, MY;

Wai-Choo Chai, Penang, MY;

Chong-Tee Ong, Penang, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 25/13 (2006.01); H01L 25/075 (2006.01); H01L 33/54 (2010.01); H01L 33/56 (2010.01); H01L 21/48 (2006.01); H01L 25/10 (2006.01); H01L 31/02 (2006.01); H01L 31/0203 (2014.01); H01L 33/48 (2010.01); H01L 33/62 (2010.01);
U.S. Cl.
CPC ...
H01L 25/13 (2013.01); H01L 21/4803 (2013.01); H01L 25/0753 (2013.01); H01L 25/0756 (2013.01); H01L 25/10 (2013.01); H01L 31/02002 (2013.01); H01L 31/0203 (2013.01); H01L 33/486 (2013.01); H01L 33/54 (2013.01); H01L 33/56 (2013.01); H01L 33/62 (2013.01); H01L 2924/0002 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0066 (2013.01);
Abstract

A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the housing base body. The recess is confined by a bottom surface and at least one side wall which are formed at least in places by the plastic material of the base body. An optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other. The optoelectronic semiconductor chip is placed in the recess, so that the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall.


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