The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Mar. 04, 2015
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventor:

Moon Soo Kim, Yongin-si, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/15184 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire.


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Kim, Moon. (2017). Semiconductor stack packages (U.S. Patent No. 9559079). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9559079

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