The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Dec. 21, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Yongchun Xin, Poughkeepsie, NY (US);

Jang H. Sim, Hopewell Junction, NY (US);

Junjing Bao, San Diego, CA (US);

Zhigang Song, Hopewell Junction, NY (US);

Yunsheng Song, Poughkeepsie, NY (US);

Assignee:

GlobalFoundries Inc., Cayman Islands, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/32055 (2013.01); H01L 21/32137 (2013.01); H01L 21/76804 (2013.01); H01L 21/76844 (2013.01); H01L 21/76846 (2013.01); H01L 21/76873 (2013.01); H01L 21/76874 (2013.01); H01L 21/76876 (2013.01); H01L 21/76879 (2013.01); H01L 23/53238 (2013.01);
Abstract

A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer.


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