The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Apr. 05, 2016
Applicant:

Magnachip Semiconductor, Ltd., Cheongju-si, KR;

Inventors:

Kwan Soo Kim, Cheongju-si, KR;

Tae Jong Lee, Cheongju-si, KR;

Kang Sup Shin, Cheongju-si, KR;

Si Bum Kim, Cheongju-si, KR;

Yang Beom Kang, Cheongju-si, KR;

Jong Yeul Jeong, Cheongju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76801 (2013.01); H01L 21/76877 (2013.01); H01L 23/485 (2013.01); H01L 23/5227 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.


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