The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Jul. 01, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Bong-Cheol Kim, Seoul, KR;

Eun-Shoo Han, Hwaseong-Si, KR;

Dong-Seok Lee, Seongnam-Si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/8234 (2006.01); H01L 21/3213 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/823431 (2013.01); H01L 27/10879 (2013.01); H01L 27/10897 (2013.01);
Abstract

A method for fabricating a semiconductor device is provided, which includes forming a first mask pattern and a second mask pattern on a first layer, forming a block mask that covers the second mask pattern on the first layer, forming first spacers on side walls of the first mask pattern, exposing the second mask pattern through removal of the first mask pattern and the block mask, forming a third mask pattern and a fourth mask pattern through etching of the first layer using the first spacers and the second mask pattern as etch masks, and forming second spacers and third spacers on side walls of the third mask pattern and side walls of the fourth mask pattern, respectively.


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