The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Oct. 01, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Anton Arriagada, San Diego, CA (US);

Chris Brindle, Poway, CA (US);

Michael A. Stuber, Carlsbad, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/46 (2006.01); H01L 21/302 (2006.01); H01L 21/20 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/84 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 27/12 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/302 (2013.01); H01L 21/2007 (2013.01); H01L 21/76254 (2013.01); H01L 21/76898 (2013.01); H01L 21/84 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 27/1203 (2013.01); H01L 29/7803 (2013.01); H01L 2224/80001 (2013.01); H01L 2224/9202 (2013.01);
Abstract

An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.


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