The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Apr. 02, 2014
Applicant:

Taiyo Yuden Co., Ltd., Tokyo, JP;

Inventors:

Masayuki Satou, Tokyo, JP;

Mitsunori Katsu, Tokyo, JP;

Hideaki Yoshida, Tokyo, JP;

Hiroyuki Kozutsumi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/418 (2006.01); G11C 8/18 (2006.01); G11C 11/419 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G11C 11/418 (2013.01); G11C 8/18 (2013.01); G11C 11/419 (2013.01); H03K 19/177 (2013.01);
Abstract

A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.


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