The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

Feb. 03, 2015
Applicant:

Vivid Engineering, Inc., San Jose, CA (US);

Inventors:

Vladislav Potanin, San Jose, CA (US);

Elena Potanina, San Jose, CA (US);

George McLean, Berkeley, CA (US);

Pavel Biryulin, Moscow, RU;

Assignee:

Vivid Engineering, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/618 (2006.01); G05F 1/575 (2006.01); G05B 13/04 (2006.01); H02M 1/08 (2006.01); H02M 3/156 (2006.01);
U.S. Cl.
CPC ...
G05F 1/618 (2013.01); G05B 13/042 (2013.01); G05F 1/575 (2013.01); H02M 1/08 (2013.01); H02M 3/156 (2013.01);
Abstract

Technologies are generally described for scaling a voltage regulator implemented as an integrated circuit (IC) that includes a power transistor configured to convert an input voltage to an output voltage, and a feedback loop configured to regulate the output voltage in response to a voltage change. At least one component of the voltage regulator may be selected for scaling, and a range of scaling factors may be identified for the component. An optimal coefficient may be determined for the scaling factors within the identified range through an empirical formulation and/or by running a circuit simulation based on parameters associated with voltage, load current, and load capacitance, for example. The optimal coefficient may be a coefficient that when applied to the component optimizes the performance of the IC and thus, the component may be scaled based on the optimal coefficient to achieve an optimized performance of the IC.


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