The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Dec. 11, 2015
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventors:

Myung-Sam Kang, Hwaseong-si, KR;

Young-Gwan Ko, Seoul, KR;

Sang-Hoon Kim, Gunpo-si, KR;

Kang-Wook Bong, Sejong-si, KR;

Hye-Won Jung, Goyang-si, KR;

Yong-Wan Ji, Gwangju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/42 (2006.01); H05K 1/03 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H05K 1/0326 (2013.01); H05K 1/0346 (2013.01); H05K 3/0023 (2013.01); H05K 3/426 (2013.01); H05K 3/428 (2013.01); H05K 2201/0129 (2013.01); H05K 2201/0154 (2013.01); H05K 2201/09827 (2013.01); H05K 2201/09854 (2013.01); H05K 2203/1476 (2013.01);
Abstract

A printed circuit board and a method of manufacturing the same are provided. The printed circuit board includes an insulating layer including a first resin layer and a second resin layer, circuit layers disposed on upper and lower surfaces of the insulating layer, and a via configured to connect the circuit layer formed on the upper surface to the circuit layer formed on the lower surface, and the second resin layer extends from an upper surface of the first resin layer to a lower surface of the first resin layer by passing through the first resin layer as to contact a side surface of the via.


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