The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Sep. 23, 2013
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Thong A. Huynh, Fremont, CA (US);

Gaoling Zou, San Jose, CA (US);

Andrea Vigna, Casanova Lonati, IT;

Mauro Ranzato, Torre D'Isola, IT;

Gianluca Mariano, San Martino Siccomario, IT;

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 7/219 (2006.01); H02M 7/06 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 7/06 (2013.01); H02M 7/219 (2013.01); H02M 2001/0009 (2013.01); H02M 2007/2195 (2013.01); Y02B 70/1408 (2013.01);
Abstract

A method is disclosed to at least partially prevent back powering of power sourcing equipment. In one or more implementations, the method includes detecting a magnitude of current through a current sensor, such as a transistor and/or a resistor. The active FET bridge is configured to rectify input power supplied by power sourcing equipment to a power over Ethernet (PoE) powered device. The method also includes causing the transistor to transition from a closed configuration to an open configuration to at least substantially prevent current flow through the transistor when the magnitude of current is below a predefined threshold to at least substantially prevent back powering of the PSE.


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