The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Nov. 23, 2015
Applicant:

Seiko Instruments Inc., Chiba-shi, Chiba, JP;

Inventors:

Hiroyuki Masuko, Chiba, JP;

Kosuke Takada, Chiba, JP;

Michiyasu Deguchi, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); H02M 3/158 (2006.01); H02M 1/36 (2007.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 3/156 (2013.01); H02M 1/36 (2013.01); H02M 3/158 (2013.01); H02M 3/1588 (2013.01); H02M 2001/0022 (2013.01);
Abstract

To provide a DC-DC converter which prevents overshoot from occurring in an output voltage even when a power supply voltage rises from a voltage lower than a desired output voltage of the DC-DC converter to a normal voltage. A DC-DC converter is equipped with a 100% DUTY detection circuit which detects a 100% DUTY state of a PWM comparator, a power supply voltage rise detection circuit which detects a rise in a power supply voltage, and a discharge control circuit which lowers an output voltage of an error amplifier. The DC-DC converter is configured to lower the output voltage of the error amplifier when a power supply voltage rise detection signal is outputted where a 100% DUTY state is reached and the output voltage of the error amplifier is higher than a predetermined voltage.


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