The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Dec. 04, 2014
Applicant:

Sandisk Technologies, Inc., Plano, TX (US);

Inventors:

Hiroyuki Kamiya, Yokkaichi, JP;

Kensuke Yamaguchi, Yokkaichi, JP;

Assignee:

SANDISK TECHOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/115 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/3065 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/0206 (2013.01); H01L 21/0217 (2013.01); H01L 21/0223 (2013.01); H01L 21/0262 (2013.01); H01L 21/02164 (2013.01); H01L 21/02247 (2013.01); H01L 21/02422 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02636 (2013.01); H01L 21/02639 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/3065 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11582 (2013.01); H01L 29/42324 (2013.01); H01L 29/7883 (2013.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01);
Abstract

A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses.


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