Semiconductor memory devices and memory systems including the same

Abstract

A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.