The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Jun. 27, 2015
Applicant:

Uniquify, Incorporated, San Jose, CA (US);

Inventors:

Jung Lee, Santa Clara, CA (US);

Mahesh Goplan, Santa Clara, CA (US);

Assignee:

Uniquify, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/22 (2006.01); G06F 1/04 (2006.01); G06F 1/12 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01); G06F 1/08 (2006.01); G11C 29/50 (2006.01); G06F 13/42 (2006.01); G11C 29/02 (2006.01); G06F 3/06 (2006.01); G06F 1/14 (2006.01); G11C 7/04 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01); G06F 3/065 (2013.01); G06F 3/067 (2013.01); G06F 3/0619 (2013.01); G06F 12/0646 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G11C 7/222 (2013.01); G11C 29/02 (2013.01); G11C 29/028 (2013.01); G11C 29/50 (2013.01); G11C 29/50012 (2013.01); G11C 7/04 (2013.01);
Abstract

A method for calibrating a read data path for a DDR memory interface circuit from time to time in conjunction with functional operation of a memory circuit is described. The method uses the steps of issuing a sequence of read commands so that a delayed dqs signal toggles continuously. Next, delaying a core clock signal originating within the DDR memory interface circuit to produce a capture clock signal. The capture clock signal is delayed from the core clock by a capture clock delay value. Next, determining an optimum capture clock delay value. The output of the read data path is clocked by the core clock. The timing for the read data path with respect to data propagation is responsive to at least the capture clock.


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