The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2017
Filed:
Sep. 14, 2011
William M. Johnson, Austin, TX (US);
Murali S. Chinnakonda, Austin, TX (US);
Jeffrey L. Nye, Austin, TX (US);
Toshio Nagata, Plano, TX (US);
John W. Glotzbach, Allen, TX (US);
Hamid R. Sheikh, Allen, TX (US);
Ajay Jayaraj, Sugarland, TX (US);
Stephen Busch, Grasse, FR;
Shalini Gupta, San Francisco, CA (US);
Robert J.p. Nychka, Canton, TX (US);
David H. Bartley, Dallas, TX (US);
Ganesh Sundararajan, Plano, TX (US);
William M. Johnson, Austin, TX (US);
Murali S. Chinnakonda, Austin, TX (US);
Jeffrey L. Nye, Austin, TX (US);
Toshio Nagata, Plano, TX (US);
John W. Glotzbach, Allen, TX (US);
Hamid R. Sheikh, Allen, TX (US);
Ajay Jayaraj, Sugarland, TX (US);
Stephen Busch, Grasse, FR;
Shalini Gupta, San Francisco, CA (US);
Robert J.P. Nychka, Canton, TX (US);
David H. Bartley, Dallas, TX (US);
Ganesh Sundararajan, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured 'on the fly' to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.