The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Jul. 24, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Hans Lee Yeager, La Jolla, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/00 (2006.01); G06F 11/00 (2006.01); G06F 1/20 (2006.01); G06F 1/28 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3203 (2013.01); G06F 1/206 (2013.01); G06F 1/28 (2013.01); G06F 1/3206 (2013.01); G06F 1/3234 (2013.01); G06F 11/3013 (2013.01); G06F 11/3058 (2013.01); G06F 11/0721 (2013.01); G06F 11/3409 (2013.01); G06F 11/3466 (2013.01);
Abstract

Systems and methods for providing local hardware limit management and enforcement are described. One embodiment includes a system for managing and enforcing hardware limits on a system on chip (SoC). The system includes a plurality of chip components provided on a system on chip (SoC). A network of local limit manager (LLM) components is distributed on the SoC. Each LLM component is in communication with a corresponding sensor module that monitors one or more of the chip components. Each LLM component comprises a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module.


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