Method and apparatus for managing estimation and calibration of non-ideality of a phase interpolator (pi)-based clock and data recovery (cdr) circuit

Abstract

A system and method for managing estimation and calibration of non-ideality of a Clock and Data Recovery circuit includes phase interpolators (PIs), first and second sets of delay elements, and a clock delay element. A first delay element of the first set of delay elements is programmed using a first digital delay control code (DDCC). The clock delay element is calibrated using a digital external delay control code (DEDCC) till a predetermined criterion is met, and is retained for subsequent use. The remaining delay elements of the first set of delay elements are separately calibrated based on the DEDCC. A first delay element of the second set of delay elements is programmed using a second DDCC. The DEDCC is readjusted for the second set of delay elements. The remaining delay elements of the second set of delay elements are separately calibrated based on the readjusted DEDCC.