The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2017
Filed:
Mar. 31, 2015
Applicant:
Xpliant, San Jose, CA (US);
Inventor:
Chirinjeev Singh, San Jose, CA (US);
Assignee:
Xpliant, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5022 (2013.01);
Abstract
System and method of checking logic equivalence following flip-flop insertions to identify paths with inversion errors. All the flip-flops in a gate-level netlist and the corresponding RTL design are treated as buffers in a logic equivalence check (LEC) tool. A logic mismatch of a path between the RTL design and the netlist indicates an odd number of inverters have been inserted in the path during a flip-flop insertion process. Accordingly, the identified path is adjusted to ensure an even number of inverters.