The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2017
Filed:
Jul. 03, 2013
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventor:
Rafael C. Camarota, San Jose, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/26 (2013.01); G01R 31/31721 (2013.01); G01R 31/31723 (2013.01); G01R 31/318505 (2013.01); G01R 31/318516 (2013.01); H03K 19/1774 (2013.01); H03K 19/17728 (2013.01); H03K 19/17772 (2013.01); H03K 19/17788 (2013.01);
Abstract
An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.