The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Aug. 14, 2013
Applicant:

Elpida Memory, Inc., Tokyo, JP;

Inventor:

Soichiro Yoshida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 19/017 (2006.01); G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); H01L 27/108 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018507 (2013.01); G11C 7/1048 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H03K 19/017 (2013.01); H01L 27/10802 (2013.01); H01L 29/7841 (2013.01); H03K 2217/0018 (2013.01);
Abstract

A semiconductor device includes a first circuit node supplied with a first signal changing between first and second logic levels, a second circuit node supplied with a second signal changing between the first and second logic levels, a third circuit node, a first transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the second and third circuit nodes, the first transistor being rendered conductive when the first signal is at the second logic level, a fourth circuit node supplied with a voltage level being close to or the same as the second logic level, and a second transistor having a gate electrically connected to the first circuit node and a source-drain path electrically connected between the third and fourth circuit nodes, the second transistor being rendered conductive when the first signal is at the first logic level.


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