The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
May. 31, 2016
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Sameer Pendharkar, Allen, TX (US);
Naveen Tipirneni, Dallas, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H01L 29/20 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H03F 3/193 (2006.01); H03F 3/195 (2006.01); H02M 5/257 (2006.01);
U.S. Cl.
CPC ...
H03K 17/6872 (2013.01); H01L 27/0883 (2013.01); H01L 27/092 (2013.01); H01L 29/2003 (2013.01); H01L 29/66446 (2013.01); H01L 29/7833 (2013.01); H02M 5/2573 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03K 17/6877 (2013.01);
Abstract
A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.