The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Jul. 08, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Vijay K. Ankenapalli, Hyderabad, IN;

Ayan Datta, Kolkata, IN;

Sumitha George, State College, PA (US);

Charudhattan Nagarajan, Bangalore, IN;

James D. Warnock, Somers, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H03K 5/134 (2014.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H03K 5/134 (2014.07); H01L 27/0886 (2013.01);
Abstract

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.


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