The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Apr. 09, 2015
Xilinx, Inc., San Jose, CA (US);
Somdutt Javre, Seoni, IN;
Pradeep Kumar Mishra, Hyderabad, IN;
Gangadhar Budde, Tq. Renapur, IN;
Siddharth Rele, Navi Mumbai, IN;
XILINX, INC., San Jose, CA (US);
Abstract
In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.