The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

May. 21, 2015
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Inventors:

Shimin Ge, Shenzhen, CN;

Hejing Zhang, Shenzhen, CN;

Chihyuan Tseng, Shenzhen, CN;

Chihyu Su, Shenzhen, CN;

Wenhui Li, Shenzhen, CN;

Longqiang Shi, Shenzhen, CN;

Xiaowen Lv, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01); H01L 29/24 (2006.01); H01L 29/49 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01); G02F 1/1333 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78648 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1288 (2013.01); H01L 29/24 (2013.01); H01L 29/4908 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); G02F 2001/133302 (2013.01); G02F 2201/123 (2013.01);
Abstract

The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (') with ion doping process, and the oxide conductor layer (′) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (), the drain () and the top gate () at the same time with one photo process; the method implements patterning process to the passivation layer () and the top gate isolation layer () together with one photo process, to reduce the number of the photo processes to five for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.


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