The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Jun. 04, 2015
Applicant:

Shenzhen Royole Technologies Co., Ltd., Shenzhen, CN;

Inventors:

Peng Wei, Shenzhen, CN;

Xiaojun Yu, Shenzhen, CN;

Zihong Liu, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 21/467 (2006.01); H01L 21/4763 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 21/0272 (2013.01); H01L 21/467 (2013.01); H01L 21/47635 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 27/1288 (2013.01); H01L 29/41733 (2013.01); H01L 29/41775 (2013.01); H01L 29/42356 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01);
Abstract

A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the substrate; sequentially depositing an insulating layer, a semiconductor layer, and a photoresist layer on the gate electrode; using the gate electrode as a photomask, exposing from a second side of the substrate and reserving the photoresist layer aligning to the gate electrode; depositing an electrode layer on the semiconductor layer and the reserved photoresist layer; stripping the reserved photoresist layer and lifting off the electrode layer stacked on the reserved photoresist layer; etching a part of the reserved electrode layer and the semiconductor layer, and forming a source electrode, a drain electrode, and a semiconductor island. The method realizes a self-alignment using the gate electrode as the photomask when forming the source, drain electrodes and the channel. Therefore, the manufacturing processes become simple and more accurate.


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