The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Nov. 17, 2015
Applicant:

SK Hynix Inc., Icheon-si, Gyeongi-do, KR;

Inventor:

Do-Young Kim, Icheon-si, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/36 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11546 (2013.01); H01L 21/265 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 29/36 (2013.01); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01);
Abstract

A method for manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention may include providing a substrate comprising a cell region and a peripheral region, wherein the peripheral region comprises an NMOS region and a PMOS region; performing a well forming ion implantation over the substrate in the cell region and the NMOS region; performing a threshold voltage adjusting ion implantation over a surface of the substrate in the cell region and the NMOS region; forming a gate pattern comprising a floating gate electrode in the cell region and the peripheral region; and performing a junction ion implantation over a surface of the cell region, wherein the floating gate electrode may have P-type conductivity.


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