The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Feb. 23, 2016
Applicant:
Stmicroelectronics (Tours) Sas, Tours, FR;
Inventor:
Olivier Ory, Tours, FR;
Assignee:
STMicroelectronics (Tours) SAS, Tours, FR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 23/528 (2006.01); H01L 21/306 (2006.01); H01L 21/304 (2006.01); H01L 21/302 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/302 (2013.01); H01L 21/3043 (2013.01); H01L 21/30604 (2013.01); H01L 21/76843 (2013.01); H01L 21/76879 (2013.01); H01L 21/78 (2013.01); H01L 29/0657 (2013.01); H01L 29/16 (2013.01);
Abstract
A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an external device. The metallization has a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate. A porous silicon region is included in the substrate to separating the second portion of the metallization from the rest of the substrate.