The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Nov. 07, 2014
Oracle International Corporation, Redwood City, CA (US);
Robert P. Masleid, Monte Sereno, CA (US);
Donald Arthur Draper, Santa Clara, CA (US);
Eben Kunz, Santa Clara, CA (US);
Laura Kocubinski, Santa Clara, CA (US);
Oracle International Corporation, Redwood City, CA (US);
Abstract
Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular 'quads.' The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g., power supply bumps, or the like), and such supply structures can supply power to the I/O circuits of the IC, while also shielding adjacent chains from each other.