Buffered automated flash controller connected directly to processor memory bus

Abstract

A mechanism is provided for direct memory access in a storage device. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism writes to the first memory buffer based on the memory command. Responsive to the buffer being full, the mechanism deterministically maps addresses from the first memory buffer to a plurality of solid state drives in the buffered flash memory module using a modular mask based on a stripe size. The mechanism builds a plurality of input/output commands to persist contents of the first memory buffer to the plurality of solid state drives according to the deterministic mapping and writes the contents of the first memory buffer to the plurality of solid state drives in the buffered flash memory module according to the plurality of input/output commands.