The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

May. 27, 2014
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Chikahiro Deguchi, Toyohashi, JP;

Yutaka Sekino, Toyohashi, JP;

Yoshiki Okumura, Kosai, JP;

Hiroaki Watanabe, Hamamatsu, JP;

Naoki Maezawa, Toyohashi, JP;

Hideyuki Negi, Hamamatsu, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); H04L 1/00 (2006.01); G06F 11/22 (2006.01); H03M 13/09 (2006.01); H03M 13/11 (2006.01); H03M 13/29 (2006.01); G06F 11/08 (2006.01); G06F 11/14 (2006.01); H03M 13/05 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1032 (2013.01); G06F 11/08 (2013.01); G06F 11/1004 (2013.01); G06F 11/108 (2013.01); G06F 11/1076 (2013.01); G06F 11/14 (2013.01); G06F 11/1629 (2013.01); G06F 11/2236 (2013.01); H03M 13/05 (2013.01); H03M 13/09 (2013.01); H03M 13/1145 (2013.01); H03M 13/1171 (2013.01); H03M 13/2903 (2013.01); H04L 1/0061 (2013.01); H04L 1/0063 (2013.01); H04L 1/0066 (2013.01);
Abstract

A semiconductor integrated circuit includes a combinational circuit to output a state value and a parity value, a first parity check circuit to perform a parity check based on the state value and the parity value stored in a first FF circuit and output a first parity error, a second parity check circuit to perform a parity check based on the state value and the parity value stored in a second FF circuit and output a second parity error, and a selector to, when the first parity error is not output but the second parity error is output, output the state value in the first FF circuit to the combinational circuit, and when the first parity error is output but the second parity error is not output, output the state value in the second FF circuit to the combinational circuit.


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