The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2017
Filed:
Jun. 26, 2015
Applicant:
Fairchild Semiconductor Corporation, San Jose, CA (US);
Inventors:
Jifa Hao, Scarborough, MA (US);
Daniel Hahn, Portland, ME (US);
Assignee:
Fairchild Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 29/063 (2013.01); H01L 29/0634 (2013.01); H01L 29/402 (2013.01); H01L 29/42368 (2013.01); H01L 29/66659 (2013.01); H01L 29/66674 (2013.01); H01L 29/66681 (2013.01); H01L 29/0653 (2013.01);
Abstract
In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.