The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Oct. 23, 2015
Applicant:

Dynax Semiconductor, Inc., Kunshan, CN;

Inventors:

Yi Pei, Kunshan, CN;

Mengjie Zhou, Kunshan, CN;

Naiqian Zhang, Kunshan, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/47 (2006.01); H01L 29/778 (2006.01); H01L 29/16 (2006.01); H01L 29/45 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/20 (2006.01); H01L 29/06 (2006.01); H01L 29/41 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41758 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/1606 (2013.01); H01L 29/20 (2013.01); H01L 29/401 (2013.01); H01L 29/452 (2013.01); H01L 29/475 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H01L 23/373 (2013.01); H01L 23/3736 (2013.01); H01L 29/2003 (2013.01); H01L 29/413 (2013.01); H01L 29/4175 (2013.01); H01L 2924/13064 (2013.01);
Abstract

A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.


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