The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jul. 12, 2012
Applicants:

Frank Hui, Irvine, FL (US);

Neal Kistler, Laguna Niguel, CA (US);

Inventors:

Frank Hui, Irvine, FL (US);

Neal Kistler, Laguna Niguel, CA (US);

Assignee:

BROADCOM CORPORATION, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 27/10 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 27/101 (2013.01); H01L 23/5252 (2013.01); H01L 23/5256 (2013.01); H01L 2924/0002 (2013.01);
Abstract

According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.


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