The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 03, 2017
Filed:
Dec. 18, 2014
Globalfoundries Inc., Grand Cayman, KY;
Brent A. Anderson, Jericho, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Robert R. Robison, Colchester, VT (US);
Andreas Scholze, Colchester, VT (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.