The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

May. 05, 2015
Applicant:

Broadcom Corporation, Irvine, CA (US);

Inventors:

Qintao Zhang, Tustin, CA (US);

Aimin Xing, Irvine, CA (US);

Assignee:

BROADCOM CORPORATION, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/167 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/26513 (2013.01); H01L 21/823807 (2013.01); H01L 21/84 (2013.01); H01L 29/0649 (2013.01); H01L 29/167 (2013.01); H01L 29/7838 (2013.01);
Abstract

Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.


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