Circuitry and method for critical path timing speculation in rams

Abstract

User data or constantly toggling functional critical path timing sensors measure delays in actual critical paths that include a RAM. Variable resistors or variable capacitors are added to RAM bit lines for redundant cells to delay bit-line sensing by sense amplifiers. The sense amplifiers' delayed data is compared to non-delayed data from normal selected RAM cells to detect timing failures. Variable resistors or capacitors may also be added between the write drivers and bit lines to delay writing data into the redundant cells. A margin delay adjustment controller sweeps margin delays for constantly toggling paths until failures. A margin delay is then adjusted and added to functional critical paths that carry user data. Functional critical path timing sensors test setup time with the added margin delay. Timing failures cause VDD to increase, while a controller reduces VDD when no failures occur. Actual delays through the RAM adjust VDD.