The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Nov. 15, 2013
Applicant:

Surecore Limited, Leeds, GB;

Inventor:

Andrew Pickering, Rugby, GB;

Assignee:

Surecore Limited, Leeds, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01);
Abstract

The present invention provides a memory unit () comprising: a storage element () comprising a pair of back to back inverters (and) having respective first and second storage access nodes (); first and second voltage lines (VSS, VDD) across which said pair of back to back inverters (and) are connected; a first access transistor (), connected to said first storage node (); a second access transistor (), connected to said second storage node (); a write word line () connected to a gate () on said first access transistor () and a gate () on said second access transistor (); a first bit line () operably connected for controllingsaid node (); a second bit line () operably connected for controlling said node (); in which there is provided a data dependent conductive path () between the first and second bit lines ().


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