The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Mar. 04, 2016
Applicant:

SK Hynix Inc., Icheon-si Gyeonngi-do, KR;

Inventor:

Sang Il Park, Suwon-si, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G11C 5/148 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01);
Abstract

A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals.


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