The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Feb. 04, 2014
Applicant:

Netronome Systems, Inc., Santa Clara, CA (US);

Inventors:

Gavin J. Stark, Cambridge, GB;

Rolf Neugebauer, Cambridge, GB;

Assignee:

Netronome Systems, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 9/46 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/109 (2013.01); G06F 9/467 (2013.01); G06F 13/385 (2013.01); G06F 2212/151 (2013.01); G06F 2212/657 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the transactional memory is enabled to do address translations and if the command is for an access (read or write) of a memory of the transactional memory, then the transactional memory performs an address translation operation on the address of the command. Parameters of the address translation are programmable and are set up before the command is received. In one configuration, certain bits of the incoming address are deleted, and other bits are shifted in bit position, and a base address is ORed in, and a padding bit is added, thereby generating the translated address. The resulting translated address is then used to access the memory of the transactional memory to carry out the command.


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